Four-Quadrant Weak Inversion Analog Multiplier in the 180nm Technology for Biomedical Applications

Seyed Alireza Khoshnevis, Farzad Shahabi, Ramin Ghadami Talkhouncheh


In this paper, a current-mode four-quadrant analog multiplier circuit is proposed that utilizes MOS translinear principle. The parameters of TSMC 0.18m technology are used to design the proposed multiplier that employs CMOS transistors operating in weak inversion region. The full combination of H-spice simulation, Monte Carlo simulation, L-edit post-layout simulation, and corner cases analysis are performed to prove its great merits of; low power consumption (1.5W), low supply voltage (0.8V), body effect immunity, wide input range (200nA), the bandwidth of 4.7 MHz, THD value lower than 2.8%, and the well-resistance of the proposed block against PVT (Technology Process, Supply Voltage, Temperature) non-idealises. The proposed architecture is compared with other current-mode week inversion multipliers indicating its noticeable superiorities over other ones particularly in FOM (Figure of Merits), consumed power and input range.


Analog Multiplier, MOS Translinear, Monte Carlo, Weak Inversion

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Bellasi, D. E., Bettini, L., Benkeser, C., Burger, T., Huang, Q., and Studer, C. (2013). VLSI design of a monolithic compressive-sensing wideband analog-to-information converter. IEEE Journal of Emerging and Selected Topics in Circuits and Systems, 3(4), pp. 552565.

Zanddizari, H., Rajan, S., and Zarrabi, H. (2018). Increasing the quality of reconstructed signal in compressive sensing utilizing Kronecker technique. Biomedical Engineering Letters, (8)2, pp. 239-248.

Mitra, D., Zanddizari, H., and Rajan, S. (2018). Improvement of signal quality during recovery of compressively sensed ECG signals. In IEEE International Symposium Medical Measurement Application in 2018 in Rome, Italy, 2018 (pp. 11-13). Italy: IEEE.

Mitra, D., Zanddizari, H., and Rajan, S. (2018). Improvement of recovery in segmentation-based parallel compressive sensings. In IEEE International Symposium on Signal Processing. and Information Technology in 2018 in Louisville, USA, Louisville, 2018 (pp. 71-76). USA: IEEE.

Ujan, S., Ghorshi, S., Pourebrahim, M., and Khoshnevis, S. A. (2016). On the Use of Compressive Sensing for Image Enhancement. In 18th International Conference on Computer Modelling and Simulation in 2016 in UK, 2016 (pp. 167-171). IEEE.

Khoshnevis, S. A., and Ghorshi, S. (2019). Enhancement of the Tomo-SAR Images Based on Compressive Sensing Method. In 6th International Conference on Space Science and Communication 2019 in Malaysia, 2019 IEEE.

Sadoghiazdi, H., and Rezaei, M. (2010). The wheatstone bridge-based aalog adaptive filter with application in echo cancellation. Analog Integrated Circuit and Signal Processing, 64(3), pp. 191-198.

Ndjountche, T., and Unbehauen, R. (1999). Improved structures for programmable filters: application in a switched capacitor adaptive filter design. IEEE transactions on analog and digital signal processing, 46(4), pp. 1137-1147.

Das, S., Babu, B. C., and Sahoo, A. K. (2012). A novel phase detection system for linear all-digital phase locked loop. In student conference on engineering and systems (SCES) in 2012 in India, 2012 (pp. 1-6). India: IEEE.

Salama. M. K., and Soliman, A. M. (2003). Low-Voltage Low-Power CMOS RF Four-Quadrant Multiplier. International Journal of Electronics and Communications (AEU), 57(5), pp. 74-78.

Spencer, R. R. (1991). Analog implementations of artificial neural networks. In IEEE International Symposium on Circuits and Systems in 1991 in Singapore, Singapore, 1991 (pp. 1271-1274). Singapore: IEEE.

Saxena, N., and Clark, J. J. (1994). A four-quadrant CMOS analog multiplier for analog neural networks. Journal of Solid- State Circuits, vol. 29(7), pp. 746-749.

Blakiewicz, G. (2009). Analog multiplier for a low-power integrated image sensor. In 16th International Conference on Mixed Design of Integrated Circuits and Systems in 2009 in Poland, 2009 (pp. 226-229). Poland: MIXDES.

Tacconi, E. J., and Christiansen, C. F. (1993). A wide range and high speed automatic gain control. In Particle Accelerator Conference in 1993 in Washington, DC, USA, 1993 (pp. 2139-2141). USA: IEEE.

Azeem, M. F., and Govilla, K. P. (2006). Design of Analog CMOS Based Fuzzy Inference System. In IEEE International Conference on Fuzzy Systems in 2006 in Vancouver, Canada, 2006 (pp. 1715-1720). Canada: IEEE.

Afrang, S., Daneshwar. M., Aminifar, S., and Yosefi, G. (2010). Implementing of Neuro-Fuzzy System with High-Speed, Low-Power CMOS Circuits in Current-Mode. In Proceedings of the 9th WSEAS International Conference on MICROELECTRONICS, NANOELECTRONICS, OPTOELECTRONICS in 2010 in USA, 2010 (pp. 61-66). USA: WSEAS.

Gilbert, B. (1968). A precise four-quadrant multiplier with sub nanosecond response. IEEE journal of solid-state circuit, 3(4), pp. 365-373.

Chaisayun, I., Piangprantong, S., and Dejhan, K. (2012). Versatile analog squarer and multiplier free from body effect. Analog Integrated Circuits and Signal Processing, 71(3), pp. 539-547.

Popa, C. (2014). Improved Accuracy Current-Mode Multiplier Circuits with Applications in Analog Signal Processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(2), pp. 443-447.

Al-Absi, M. A., Hussein, A., and TaherAbuelmaatti, M. (2013). A Low Voltage and Low Power Current-Mode Analog Computational Circuit, Circuits, Systems, and Signal Processing, 32(2), pp. 321-331.

Leenaerts, D. M. W., Joordens, G. H. M., and Hegt, J. H. (1996). A 3.3 V 625 kHz switched-current multiplier. IEEE journal of solid-state circuit, 31(2), pp. 1340-1343.

Purushothaman, S. (2008). A simple 4 quadrant NMOS analog multiplier with input range equal to VDD and very low THD. In IEEE International Conference on Electro/Information Technology in 2008 in Ames, USA, 2008 (pp. 134-139). USA: IEEE.

Aksin, D. Y., Basyurt, P. B., and Uyanik, H. U. (2009). Single-ended input four-quadrant multiplier for analog neural networks. In European Conference on Circuit Theory and Design in 2009 in Turkey, 2009 (pp. 307 310). Turkey: IEEE.

Seevinck. E., and Wiegerink, R. J. (1991). Generalized Translinear Principle. IEEE journal of solid-state circuit, 26(1), pp. 1098-1102.

Serrano-Gotarredona, T., Linares-Barranco, B., and Andreou, A. G. (1999). A general translinear principle for subthreshold MOS transistors. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 46(2), pp. 607-616.

Danesh, MH., Mahmoudian, E., Fard, AE. (2013). A new current-mode squarer circuit for RMS-to-DC converter. International Journal of Engineering and Innovative Technology (IJEIT), 3(2) pp. 1-4.

Kasimis, C., and Psychalinos, C. (2011). 0.65V class-AB current-mode four-quadrant multiplier with reduced power dissipation. International Journal of Electronics and Communications (AEU), 65(4), pp. 673677.

Izadi, V., Abedi, M., and Bolandi, H. (2016). Verification of reaction wheel functional model in HIL test-bed. In 2016 4th International Conference on Control, Instrumentation, and Automation (ICCIA) in 2016 in Iran, 2016 (pp. 155-160). IEEE: Iran.

Izadi, V., Abedi, M., and Bolandi, H. (2017). Supervisory algorithm based on reaction wheel modelling and spectrum analysis for detection and classification of electromechanical faults. IET Science, Measurement & Technology, 11(8), pp.1085-1093.

Gravati, M., Ferri, G., Valle, M., Guerrini, N., and Reyes, N. (2005). A novel current-mode very low power analog CMOS four quadrant multiplier. In proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC) in 2005 in France, 2005 (pp. 495-498). France: IEEE.

Mahmoudi, A., Khoei, A., and Hadidi, K. (2007). A Novel Current-Mode Micropower Four Quadrant CMOS Analog. In IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC) in 2007 in Taiwan, 2007 (pp. 321-324). Taiwan: IEEE.

Nikseresht, S., Azhari, SJ., and Danesh, M. (2017). High bandwidth four-quadrant analog multiplier. In Iranian Conference on Electrical Engineering (ICEE) in 2017 in Tehran, Iran, 2017 (pp. 210-215). Iran: IEEE.

Danesh, M., Jayaraj, A., Chandrasekaran, ST., and Sanyal, A. (2019). Ultra-Low Power Analog Multiplier Based on Translinear Principle. In IEEE International Symposium on Circuits and Systems (ISCAS) in 2019 in Japan, 2019. Japan: IEEE.

Razavi, B. (2001). Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill.

Enz, C. C., Krummenacher, F., and Vittoz, E. A. (1995). An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications. Analog Integrated Circuits and Signal Processing, 8(3), pp. 83-114.

Lpez-Martn, A. J., and Carlosena, A. (2001). Current-Mode Multiplier/Divider Circuits Based on the MOS Translinear Principle. Analog Integrated Circuits and Signal Processing, 28(1), pp. 265-278.


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